MYR4,000 - MYR5,000 Per Month
Melaka City, Melaka
Be an early applicant!
Posted 2 months ago • Closing 5 May 2024
Be an early applicant!
Requirements
- Master Degree in Electronic Engineering,
- Fluent spoken and written English & Mandarin.
- Working experience in asic area is preferred;
- Expertise in HDL programming, logic synthesis, clock trees optimization, design for testability (DFT), digital synthesis, timing analysis, debug and validation;
- Professional and pleasant personality with good written and verbal communication and interpersonal skills;
- Able to work under tight deadlines in a fast paced environment.
Responsibilities
- Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies;
- Development of front-end implementation tasks, such as VHDL/Verilog coding, synthesis, timing simulations and logic equivalence checks;
- Management of Back-end phase (place & route phase and post layout simulation);
- Responsible for validating and qualifying components through simulation, hardware emulation and laboratory equipment;
- Pre-layout and post-layout functional and timing problem solver.
Benefits
- 5 working day
- Medical claims
- Access to training and education in ASIC design.
- EPF
- SOCSO
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