To lead technically in ASIC design implementation domain, which may include stages from design architectural understanding till timing signoff for tapeout
To develop and signoff I.C. design projects RTL2GDS implementation and flow improvement.
Architectural and micro-architectural intent understanding
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Management of product sustaining activities which include driving product performance improvement (yield, test time, quality, etc.) and cost reduction.
Manage the introduction of new products (NPI) and their ramp to volume manufacturing.
Work with the Manufacturing, Design, Quality, and Failure Analysis teams in the disposition of product excursions and manage cases through a material review board.
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Celestica is seeking a Senior Lead Engineer, Hardware Design (CPLD) in Penang to drive architecture, RTL design and back-end flow for high-performance FPGA/CPLD systems.
You will collaborate with system, hardware and software teams, deliver test plans, verify designs, and mentor junior engineers while maintaining schedule milestones. Strong Verilog/SystemVerilog and tool experience (ISE, Vivado, Quartus) are essential for success.
Understand design data flow and complexity, translating to physical design constraints and strategy for convergence with best PPA metrices.
Strategize floor-planning options and experimentation, fine tune Place & Route for design specific needs and close timing requirement within given power envelope.
Implement Low Power physical design flows and methodologies such as Power-Gating, Clock-Gating and MBR flows.
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Understand design data flow and complexity, translating to physical design constraints and strategy for convergence with best PPA metrices.
Strategize floor-planning options and experimentation, fine tune Place & Route for design specific needs and close timing requirement within given power envelope.
Implement Low Power physical design flows and methodologies such as Power-Gating, Clock-Gating and MBR flows.
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Support systematic problem-solving methodologies to resolve complex product and process quality issues across the product lifecycle.
Provide quality engineering assessment on cross-functional new product development teams, ensuring robust design inputs, verification and validation strategies and regulatory compliance.
Drive the implementation and continuous improvement of risk management activities, including hazard analysis, fault tree analysis and FMEAs, ensuring alignment with ISO 14971 and internal standards.
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Support systematic problem-solving methodologies to resolve complex product and process quality issues across the product lifecycle.
Provide quality engineering assessment on cross-functional new product development teams, ensuring robust design inputs, verification and validation strategies and regulatory compliance.
Drive the implementation and continuous improvement of risk management activities, including hazard analysis, fault tree analysis and FMEAs, ensuring alignment with ISO 14971 and internal standards.
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Altera, based in Penang, Malaysia, is seeking an experienced Design Verification (DV) Engineer to verify DFT and test-related logic for complex SoCs on our flagship FPGAs. You will develop and execute pre-silicon verification plans, build UVM-based testbenches, and ensure silicon quality through rigorous verification methodologies.
Ideal candidates hold 5+ years of ASIC/SoC verification, strong SystemVerilog/UVM expertise, and hands-on experience with DFT features such as scan, MBIST, LBIST, and