Understand design data flow and complexity, translating to physical design constraints and strategy for convergence with best PPA metrices.
Strategize floor-planning options and experimentation, fine tune Place & Route for design specific needs and close timing requirement within given power envelope.
Implement Low Power physical design flows and methodologies such as Power-Gating, Clock-Gating and MBR flows.
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Understand design data flow and complexity, translating to physical design constraints and strategy for convergence with best PPA metrices.
Strategize floor-planning options and experimentation, fine tune Place & Route for design specific needs and close timing requirement within given power envelope.
Implement Low Power physical design flows and methodologies such as Power-Gating, Clock-Gating and MBR flows.
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Perform pre-Si verification on various IP blocks and full-chip of FPGA/ASIC designs.
The job scope includes test plan definition, SystemVerilog/UVM test bench and content development, debugging and running regression to deliver good-quality design.
Candidate will work closely with team and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure high quality design validation.
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Support systematic problem-solving methodologies to resolve complex product and process quality issues across the product lifecycle.
Provide quality engineering assessment on cross-functional new product development teams, ensuring robust design inputs, verification and validation strategies and regulatory compliance.
Drive the implementation and continuous improvement of risk management activities, including hazard analysis, fault tree analysis and FMEAs, ensuring alignment with ISO 14971 and internal standards.
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Support systematic problem-solving methodologies to resolve complex product and process quality issues across the product lifecycle.
Provide quality engineering assessment on cross-functional new product development teams, ensuring robust design inputs, verification and validation strategies and regulatory compliance.
Drive the implementation and continuous improvement of risk management activities, including hazard analysis, fault tree analysis and FMEAs, ensuring alignment with ISO 14971 and internal standards.
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Altera, based in Penang, Malaysia, is seeking an experienced Design Verification (DV) Engineer to verify DFT and test-related logic for complex SoCs on our flagship FPGAs. You will develop and execute pre-silicon verification plans, build UVM-based testbenches, and ensure silicon quality through rigorous verification methodologies.
Ideal candidates hold 5+ years of ASIC/SoC verification, strong SystemVerilog/UVM expertise, and hands-on experience with DFT features such as scan, MBIST, LBIST, and
We are looking for a Mechanical Engineer to join our engineering team in Penang. You will work closely with customers, suppliers, production, and project teams to develop mechanical designs, prepare engineering documentation, support prototype development, and ensure projects are delivered on time, within quality standards, and according to customer requirements.
Circuit Board Innovation: Lead the conceptualization, design, and prototyping of next-generation IoT PCB boards specifically for commercial vehicle tracking.
Hardware Experimentation: Conduct rigorous experimentation on circuit performance, signal integrity, and sensor integration to ensure reliability in harsh automotive environments.
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