Own Power Integrity (PI) signoff for advanced-node ASIC/SoC designs including advanced package, covering Static IR Drop, Dynamic IR Drop, Electromigration (EM), Power Grid Analysis, In-rush Current, Power-up/Power-down analysis, Load Step/Transient analysis, and Package/Board/PDN co-analysis.
Lead full-chip and block-level power integrity analysis from early design through tapeout, including power delivery network modeling, power-domain analysis, vectorless and vector-based simulation, and PI signoff methodology and closure.
Drive early-stage PI methodology and flow bring-up, especially for new process nodes, early PDKs, immature technology files, and new power architectures.
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