Utilize the latest tools and methodologies such as UVM to develop state-of-the-art verification environments for verifying the functionalities of automotive Ethernet switches
Formulate and develop coverage-driven, constrained random tests to identify and catch pre-silicon design bugs
Collaborate with design engineers and verification architects to design test plans, coverage models, and test suites that improve chip quality and satisfy automotive customer requirements
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Utilize the latest tools and methodologies such as UVM to develop state-of-the-art verification environments for verifying the functionalities of automotive Ethernet switches
Formulate and develop coverage-driven, constrained random tests to identify and catch pre-silicon design bugs
Collaborate with design engineers and verification architects to design test plans, coverage models, and test suites that improve chip quality and satisfy automotive customer requirements
...
Own the end-to-end Test Hardware Development Flow, including design specification, implementation, review, sign-off, debugging, troubleshooting, and follow-up support for Automotive Microcontroller Testing
Design both Production Test Hardware (e.g. Probecard, Loadboard, Burn-in Board) and Characterization Test Hardware
Ensure On-Time Delivery (OTD) and First-Time-Right (FTR) of all Test Hardware deliverables
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Own the end-to-end Test Hardware Development Flow, including design specification, implementation, review, sign-off, debugging, troubleshooting, and follow-up support for Automotive Microcontroller Testing
Design both Production Test Hardware (e.g. Probecard, Loadboard, Burn-in Board) and Characterization Test Hardware
Ensure On-Time Delivery (OTD) and First-Time-Right (FTR) of all Test Hardware deliverables
...
Perform RTL-to-gate synthesis using EDA tools such as Synopsys Design Compiler/Fusion Compiler or Cadence Genus to generate optimized gate-level netlists.
Run Static Timing Analysis (STA) including setup/hold checks across pre- and post-layout stages using tools such as Synopsys PrimeTime or Cadence Tempus.
Collaborate with design, verification, and PD teams to ensure timing closure and design optimization.
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Perform RTL-to-gate synthesis using EDA tools such as Synopsys Design Compiler/Fusion Compiler or Cadence Genus to generate optimized gate-level netlists.
Run Static Timing Analysis (STA) including setup/hold checks across pre- and post-layout stages using tools such as Synopsys PrimeTime or Cadence Tempus.
Collaborate with design, verification, and PD teams to ensure timing closure and design optimization.
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