Processor silicon DDR interface feature enablement, electrical test and debug engineer. In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & feature enable, & debugs electrical issues in the memory sub-system of new processors.
Develop, manage, and update detailed MEP cost plans, budgets, and forecasts
Conduct cost benchmarking and value engineering for critical building systems (HVAC, cleanroom environments, electrical infrastructure, ELV, BMS, etc.)
Support design teams by providing cost advice during design development stages...