Work and interact with a wide variety of NI staff in R&D software and hardware organizations, as well as employees from other business groups, in Austin, Texas, Debrecen, Hungary and Penang, Malaysia.
Validate automated test solutions (using Gage R & R, as well as other methods) for the manufacture of test and measurements instruments and hold required reviews to assure test system readiness for product release.
Full ownership of test solutions after deployment on production floor. Ensure test solutions owned are in good condition and readily available for NI Operations and Services.
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Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
Perform design IP Implementation, IR drop analysis, DFT, STA and foundry merge.
Work with manager to achieve assigned tape out target.
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Use industry standard electrical design tools to design, simulate, and verify board level analog circuits for test and measurement applications, including: Linear power supplies
Switched mode power supplies (DC–DC)
High precision/highspeed analog front ends (including ADCs, DACs, amplifiers)
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Research and propose alternative parts with effective solutions in consideration of avoiding major software & product calibration, hardware topology changes to replace EOL parts in NI products.
Implement and simulate designs through CAD and synthesis tools. i.e. Mentor Graphics.
Verify and validate designs of hardware re-designs. Debug any issues that may arise.
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Use industry standard electrical design tools to design, simulate, and verify board level analog circuits for test and measurement applications, including: Linear power supplies
Switched mode power supplies (DC–DC)
High precision/highspeed analog front ends (including ADCs, DACs, amplifiers)
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Responsible for Physical Design tasks at block or subsystem level. The tasks will include Floorplanning, Synthesis, Placement, CTS, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.
Owning the entire process from SYN to PNR using Synopsys Fusion Compiler. Crafted the convergence recipe & design collateral to meet project requirement.
Run signoff flow including PV, extraction, STA, VCLP, FEV and EMIR, analyse the violation and converge the design.
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