- Singapore
Full Time IC Design Engineer (Design Verification) Jobs, Salary up to SGD 6,000 in AUREXIS TECH PTE. LTD. - Maukerja
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Responsibilities
Job Description
Assist in Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications.
Support the development and maintain SystemVerilog/ UVM-based verification environments and testbenches
Develop directed and constrained-random tests, assertions(SVA), and functional coverage.
Assist in Debug DUT issues, analyze simulation results, and drive verification closure.
Collaborate with cross-functional teams throughout the design and verification lifecycle.
Support regression automation and continuously improve verification methodologies.
Leverage AI-assisted tools and data-driven techniques to enhance verification efficiency, coverage, and debug productivity.
Requirements
Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or related field
Knowledge in ASIC/SoC/IP verification using SystemVerilog and UVM.
Knowledge of constrained-random verification, assertions (SVA), functional coverage, and scripting languages such as Python/ Perl/ Tcl.
Experience using industry-standard EDA tools (e.g., Cadence or Synopsys).
Familiarity with AI/ML-assisted EDA tools or the use of generative AI to improve verification workflows is an advantage.
Strong analytical, problem-solving, and communication skills.
We invite qualified candidates to apply online or submit a detailed resume to *************
.
Assist in Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications.
Support the development and maintain SystemVerilog/ UVM-based verification environments and testbenches
Develop directed and constrained-random tests, assertions(SVA), and functional coverage.
Assist in Debug DUT issues, analyze simulation results, and drive verification closure.
Collaborate with cross-functional teams throughout the design and verification lifecycle.
Support regression automation and continuously improve verification methodologies.
Leverage AI-assisted tools and data-driven techniques to enhance verification efficiency, coverage, and debug productivity.
Requirements
Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or related field
Knowledge in ASIC/SoC/IP verification using SystemVerilog and UVM.
Knowledge of constrained-random verification, assertions (SVA), functional coverage, and scripting languages such as Python/ Perl/ Tcl.
Experience using industry-standard EDA tools (e.g., Cadence or Synopsys).
Familiarity with AI/ML-assisted EDA tools or the use of generative AI to improve verification workflows is an advantage.
Strong analytical, problem-solving, and communication skills.
We invite qualified candidates to apply online or submit a detailed resume to *************
.
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