- 1 YISHUN AVENUE 7 North Region (Singapore) Singapore

Working Location
Job Description
Responsibilities
The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.
In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.
Requirements:
IC Layout
Job description:
IC Layout
Skill Set (Mem)
Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
Good experience in Floor-planning, hierarchy layout and chip integration.
Experience in memory compiler will be a plus.
Knowledge of Script Programming and SKILL Programming would be a plus.
Able to lead or train a team of junior engineers
Good knowledge of memory layout topology.
Ability to lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
Self-reliant, with the ability to work independently as well as in a team.
Good leadership quality in project management.
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