Full Time Senior CPLD-FPGA Hardware Design Lead Jobs, in Celestica Pulau Pinang - Maukerja

Celestica is seeking a Senior Lead Engineer, Hardware Design (CPLD) in Penang to drive architecture, RTL design and back-end flow for high-performance FPGA/CPLD systems.

You will collaborate with system, hardware and software teams, deliver test plans, verify designs, and mentor junior engineers while maintaining schedule milestones. Strong Verilog/SystemVerilog and tool experience (ISE, Vivado, Quartus) are essential for success.