Job Summary
Our Client is looking for experienced Physical Design Engineers to join their semiconductor engineering team. The role responsible for block-level and/or full-chip physical implementation from netlist through GDSII/tape-out, with strong ownership of timing closure, physical verification and signoff activities
Our client is a advanced semiconductor designs, including high-performance and low-power SoCs and complex IP/subsystems
Key Responsibilities
- Own and execute block-level and/or full-chip Physical Design from netlist to GDSII
- Perform: Floor planning & Power planning & Placement and optimization & Clock Tree Synthesis (CTS) & Routing & Post-route optimization
- Drive timing closure across multiple modes and corners (MCMM), including setup and hold
- Analyze and resolve: Timing violations & Signal Integrity (SI) & Power-related issues & Physical design violations
- Perform DRC/LVS and physical verification activities and ensure signoff quality
- Perform IR Drop and Electromigration (EM) analysis
- Work closely with STA, RTL, DFT, Verification and other cross-functional teams.
- Collaborate with STA teams on setup/hold closure and ECO implementation.
- Support tape-out and customer deliverables.
- Participate in design reviews and contribute to improvement of physical design flows and methodologies.
- For senior-level candidates, provide technical guidance and mentoring to junior engineers.
Requirements
- Bachelor's in Electrical & Electronic Engineering, Electronics Engineering, Computer Engineering, or related field
- At lease 4-years and above experience in Engineering or related field. Fresh graduate are welcome to apply.
- Experience in RTL/netlist-to-GDSII physical implementation
- Experience working with advanced/low technology nodes is highly preferred
- Strong analytical and problem-solving skills