As technical lead of PNP, leading new feature test method development, feature enablement, feature validation & issue debugging.
Closely interact with feature architect, silicon design and FW team in test planning, execution & debug, as well as in feature definition for future product generation.
Develop comprehensive functionality & stability test plans for PNP validation of processors.
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Collaborate with all IP designers to ensure that tasks required for generating power numbers and developing power models are properly planned which include custom layout IP and ASIC IP
Develop power models that cover multiple IPs and operating modes; this requires familiarity with schematic design, SPICE simulation, reading Liberty files, and analyzing power reports
Understand IP functionality to define power estimation methodologies (vector-based or vector less) according to software requirements
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