Define the overall architecture of LPU chips based on a static dataflow architecture, including compute array design and on-chip SRAM memory hierarchy planning, to address latency and data movement challenges in large model inference.
Collaborate with compiler engineers to define hardware microarchitecture and enable hardware-software co-design, ensuring efficient scheduling strategies before tape-out.
Build architectural models to evaluate compute performance, memory bandwidth, latency, and power consumption, and benchmark LPU architecture against GPU and NPU architectures.
...
Ensure timely delivery of projects within the committed schedule and budget ensuring project issues are timely resolved or escalated to management for attention.
Provide regular update to HTX management on the project progress highlighting project milestones, issues and track project expenditure.
Effectively engage and manage all relevant stakeholders to deliver system.
...
Pursuing a Master’s or PhD degree in EE is preferred
Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must
Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
...