Drive NAND development from pre-silicon (circuit simulation for stress/screen test method), 1st silicon to qualification from DPPM (Defective part per million) perspective.
Own and achieve DPPM (Defective part per million) targets on SD NAND Technology in line with technology & product roadmaps.
Develop and define test strategy and test flow for SD NAND Technology on DOEs from dedicated Memory Health R&D line.
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Drive NAND development from pre-silicon (circuit simulation for stress/screen test method), 1st silicon to qualification from DPPM (Defective part per million) perspective.
Own and achieve DPPM (Defective part per million) targets on SD NAND Technology in line with technology & product roadmaps.
Develop and define test strategy and test flow for SD NAND Technology on DOEs from dedicated Memory Health R&D line.
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Provides DDR technical leadership in the development of new test & validation features
Closely interacts with silicon design (DRAM controller and memory Phy) in test execution & debug, as well as in feature definition for future product generation
Writes comprehensive electrical & functional test plans for the memory validation of processors
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