Architecture specifications for the SoC’s peripheral subsystems: micro-architecture definition, flow and sequence diagrams, power and performance models, and pseudocode — the documents RTL design and verification teams implement from
Off-die interface definition — modes, electrical and protocol behavior, and integration requirements that account for boards, cables, connectors, PHYs, and the software driver model
Debug at RTL and gate level with the design team when implementation raises questions the specification must answer
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FPGA Prototyping & Development – Develop, implement and bring up FPGA images for SoC pre-silicon prototyping, supporting Design Verification, Software Development, Validation and System Test teams.
RTL& FPGA Implementation – Modify and debug RTL for FPGA implementation taking designs from RTL through synthesis, place-and-route and bitstream generation using Xilinx Vivado/ISE and Intel Quartus Prime Pro.
Timing& Performance Optimization – Define and implement FPGA timing constraints, perform timing analysis and optimize designs for performance, throughput, resource utilization and reliable FPGA builds.
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Architecture specifications for the SoC’s peripheral subsystems: micro-architecture definition, flow and sequence diagrams, power and performance models, and pseudocode — the documents RTL design and verification teams implement from
Off-die interface definition — modes, electrical and protocol behavior, and integration requirements that account for boards, cables, connectors, PHYs, and the software driver model
Debug at RTL and gate level with the design team when implementation raises questions the specification must answer
...