Qa Engineer Jobs in Bayan Lepas - July 2026 - Urgent Hiring
Paparan 74 hasil carian kerja kosong untuk
"qa engineer"
di Bayan Lepas
Jangan lepaskan peluang untuk kerja Qa Engineer terkini! di Bayan Lepas
Urus Pemberitahuan
Undisclosed
- Scope and Define tasks: Test and sample arrangement follow priority which to meet the delivery deadline for production or R&D product.
- Tool Operation: Operate microscope, mini-chamber, MST(Media Servo Tester), blade tester, also to ensure high-quality test is perform.
- Tool maintenance: manage spare parts inventory, perform PM within schedule, troubleshoot blade tester and mini-chamber. ...
Posted
14 days ago
Undisclosed
- To assist the IQA Supervisor to ensure that IQA daily activities are carried out smoothly.
- To ensure that the turnaround time for receiving inspection is done within the goal set by the IQA Supervisor.
- Receiving inspection and data collection of incoming materials on FIFO basis. ...
Posted
17 days ago
Undisclosed
- To assist the IQA Supervisor to ensure that IQA daily activities are carried out smoothly.
- To ensure that the turnaround time for receiving inspection is done within the goal set by the IQA Supervisor.
- Receiving inspection and data collection of incoming materials on FIFO basis. ...
Posted
17 days ago
Undisclosed
- Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
- Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
- Perform quality checks on timing models to confirm all timing arcs meet software requirements. ...
Posted
17 days ago
Undisclosed
- Drive full-chip and block-level physical implementation, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
- Perform timing closure across multi-corner, multi-mode (MCMM) conditions, ensuring compliance with performance, power, and area (PPA) goals.
- Conduct static timing analysis (STA) using PrimeTime or equivalent tools, including timing ECO implementation and signoff validation. ...
Posted
17 days ago
Undisclosed
- Responsible for Physical Design tasks at block or subsystem level. The tasks will include Floorplanning, Synthesis, Placement, CTS, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.
- Owning the entire process from SYN to PNR using Synopsys Fusion Compiler. Crafted the convergence recipe & design collateral to meet project requirement.
- Run signoff flow including PV, extraction, STA, VCLP, FEV and EMIR, analyse the violation and converge the design. ...
Posted
6 days ago
Undisclosed
- Executing high density package layout designs across client’s product portfolios (Test Chips, CPUs, Chipsets, SoC designs, Test Vehicles and more)
- IC package layout design including feasibility studies, substrate layout design/routing, package stack up, ballmap etc.
- Perform DRC checks, unconnected pins and dangling trace/vias and fix the design accordingly. ...
Posted
7 days ago
Undisclosed
- To define and develop a general-purpose measurement solution to meet customer and market demands.
- To define the system architecture and capture requirements for the new measurement solutions.
- To collaborate with different team to ensure the product meets system requirements. ...
Posted
11 days ago
Undisclosed
- Leads the architecture, design and implementation of technical solutions in multiple market segments that meet customer and regulatory requirements.
- Collaborate closely with cross-functional teams, suppliers, and customers to develop world class products in highly regulated markets.
- Familiar with EE development processes & workflows to realize products on a PCBA and product/system level. ...
Posted
14 days ago
Undisclosed
- Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
- Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
- Perform quality checks on timing models to confirm all timing arcs meet software requirements. ...
Posted
a month ago
Undisclosed
- Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
- Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
- Perform quality checks on timing models to confirm all timing arcs meet software requirements. ...
Posted
a month ago
Undisclosed
- To define and develop a general-purpose measurement solution to meet customer and market demands.
- To define the system architecture and capture requirements for the new measurement solutions.
- To collaborate with different team to ensure the product meets system requirements. ...
Posted
25 days ago
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