Use industry standard electrical design tools to design, simulate, and verify board level analog circuits for test and measurement applications, including: Linear power supplies
Switched mode power supplies (DC–DC)
High precision/highspeed analog front ends (including ADCs, DACs, amplifiers)
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Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
Perform design IP Implementation, IR drop analysis, DFT, STA and foundry merge.
Work with manager to achieve assigned tape out target.
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Responsible for Physical Design tasks at block or subsystem level. The tasks will include Floorplanning, Synthesis, Placement, CTS, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.
Owning the entire process from SYN to PNR using Synopsys Fusion Compiler. Crafted the convergence recipe & design collateral to meet project requirement.
Run signoff flow including PV, extraction, STA, VCLP, FEV and EMIR, analyse the violation and converge the design.
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Responsible for Physical Design tasks at block or subsystem level. The tasks will include Floorplanning, Synthesis, Placement, CTS, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.
Owning the entire process from SYN to PNR using Synopsys Fusion Compiler. Crafted the convergence recipe & design collateral to meet project requirement.
Run signoff flow including PV, extraction, STA, VCLP, FEV and EMIR, analyse the violation and converge the design.
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