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Qa Technician Jobs in Pulau Pinang - September 2026 - Urgent Hiring
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Undisclosed
- Responsible for implementing RTL-to-GDSII process flow for block-level or full-chip SoCs.
- Communicate closely with the front-end design team to ensure the physical feasibility of the design modules.
- Analyze the backend design process for timing and congestion and optimize PPA from an implementation perspective. ...
Posted
17 days ago
Undisclosed
- Drive full-chip and block-level physical implementation, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
- Perform timing closure across multi-corner, multi-mode (MCMM) conditions, ensuring compliance with performance, power, and area (PPA) goals.
- Conduct static timing analysis (STA) using PrimeTime or equivalent tools, including timing ECO implementation and signoff validation. ...
Posted
8 days ago
Undisclosed
- Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
- Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning, layout construction, physical verification and QA flow sign-off.
- Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project. ...
Posted
19 days ago
MYR3,500 - MYR5,000 Per Month
- Operate and monitor Dicing and Pick & Place machines according to work instructions and process specifications.
- Perform machine setup, product changeover, parameter adjustment, and first-piece verification.
- Monitor machine and process parameters during production. ...
Posted
2 days ago
Undisclosed
- Free Daily Meals – Enjoy complimentary breakfast and lunch on every working day.
- Insurance Coverage for You & Your Family – Enjoy comprehensive insurance benefits that provide added protection for you and your loved ones.
- Medical & Dental Benefits – Enjoy coverage that supports your health and well-being. ...
Posted
13 days ago
Undisclosed
- Perform the design and development of multi-layer package substrates (8+ layers) for advanced semiconductor devices.
- Perform package layout, routing, and stack-up planning using EDA tools (Mentor Graphics, Cadence Allegro, PLA).
- Ensure designs comply with substrate manufacturing rules (trace width/spacing, via design, impedance requirements). ...
Posted
15 days ago
Undisclosed
- Strong skills in Physical Design, including floorplanning, placement, CTS, routing, and timing closure for complex SoCs.
- Proficiency in Physical Verification, covering DRC, LVS, antenna checks, and reliability signoff at advanced technology nodes.
- Solid foundation in Logic Design and Circuit Design, with understanding of digital design fundamentals, clocking, and low-power techniques. ...
Posted
23 days ago
Undisclosed
George Town
- Lead a high-performing team of IC Design Engineers in the end-to-end development of Motion Control Sensor ASICs.\
- Oversee technical architecture, design development, people management, and full-lifecycle project execution.
- Thrive in a fast-paced, start-up-like environment, responsible for all ASIC deliverables. ...
Posted
23 days ago
Undisclosed
Malaysia
- Own and support Physical Verification (DRC/LVS/ERC) and Parasitic Extraction (PEX) flows in a custom layout environment
- Maintain and improve PV/PEX flows across multiple technology nodes
- Build and maintain regression testbenches to ensure tool/flow quality ...
Posted
a month ago
Undisclosed
- Working on 10nm/7nm/5nm or lower nodes designs with various customers.
- Responsible to understand and develop flow/methodology using Perl/TCL programming for PnR activities (Floor planning, Placement, CTS, and Routing).
- Expertise in solving lower node technology related problems for critical designs to achieve desired performance, area, and power targets. ...
Posted
17 days ago
Undisclosed
- Use industry standard electrical design tools to design, simulate, and verify board level analog circuits for test and measurement applications, including: Linear power supplies
- Switched mode power supplies (DC–DC)
- High precision/highspeed analog front ends (including ADCs, DACs, amplifiers) ...
Posted
20 days ago
Undisclosed
- Lead and own the physical design flow from RTL - GDSII for complex sub-systems consisting of several blocks.
- Drive floorplanning, power planning, placement, clock tree synthesis (CTS), routing and signoff (timing, IR, EM, DRC/LVS)
- Handle sub-system level PD and provide necessary feedback to full-chip owner. ...
Posted
22 days ago
Undisclosed
- To define and develop a general-purpose measurement solution to meet customer and market demands.
- To define the system architecture and capture requirements for the new measurement solutions.
- To collaborate with different team to ensure the product meets system requirements. ...
Posted
23 days ago
Undisclosed
Malaysia
- Design, simulate, and optimize high-performance analog and mixed-signal circuits.
- Develop and implement high-speed interface circuits, including Serializer/Deserializer (SerDes), DDR I/O, and other high-speed I/O designs.
- Design and verify clocking circuits such as PLLs, DLLs, and high-speed clock distribution networks. ...
Posted
24 days ago
Undisclosed
Malaysia
- Perform full-custom layout design for analog and mixed-signal circuits using Cadence layout tools.
- Develop layouts for high-speed I/O circuits, including SerDes, DDR I/O, and other high-speed interfaces.
- Implement layouts for analog IPs such as PLLs, DLLs, LDOs, Bandgap References, and other precision analog circuits. ...
Posted
24 days ago
Undisclosed
- Responsible for implementing RTL-to-GDSII process flow for block-level or full-chip SoCs.
- Communicate closely with the front-end design team to ensure the physical feasibility of the design modules.
- Analyze the backend design process for timing and congestion and optimize PPA from an implementation perspective. ...
Posted
a month ago
Undisclosed
- Custom Layout Engineer
- Bayan Lepas, Penang
- Location: Bayan Lepas, Penang, Malaysia ...
Posted
a month ago
Undisclosed
- Drive full-chip and block-level physical implementation, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
- Perform timing closure across multi-corner, multi-mode (MCMM) conditions, ensuring compliance with performance, power, and area (PPA) goals.
- Conduct static timing analysis (STA) using PrimeTime or equivalent tools, including timing ECO implementation and signoff validation. ...
Posted
a month ago
Undisclosed
- Candidate must possess at least a Bachelor's Degree or Master's in Engineering (Electrical/Electronic) or equivalent
- Candidate who loves to work with FPGA and proficient in Altera Quartus II or Xilinx Vivado software tools
- Experienced in intense FPGA development and proficient in ModelSim is a huge advantage ...
Posted
a month ago
Undisclosed
George Town
- The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure
- The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high-speed designs at the latest technology nodes.
- The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development. ...
Posted
a month ago
Undisclosed
- Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
- Perform design IP Implementation, IR drop analysis, DFT, STA and foundry merge.
- Work with manager to achieve assigned tape out target. ...
Posted
a month ago
Undisclosed
Malaysia
- Design and develop high-performance analog and mixed-signal circuits for advanced SoCs.
- Design and optimize high-speed I/O interfaces such as SerDes I/O, DDR I/O, or other high-speed interface circuits.
- Design and validate PLL, DLL, and high-speed clock distribution circuits. ...
Posted
a month ago
Undisclosed
Malaysia
- Design, implement, and maintain high performance C++ services handling high message rates and low latency workloads.
- Optimize existing components for latency, throughput, and CPU/memory efficiency.
- Develop and tune networking, messaging, and I/O layers to handle large data volumes reliably. ...
Posted
20 days ago
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