Qc Engineer Jobs in Bayan Lepas - August 2026

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Showing 66 jobs results for "qc engineer" in Bayan Lepas

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Physical Design Engineer Physical Design Engineer

UST Malaysia

Undisclosed

Full Time

Bayan Lepas

Drive full-chip and block-level physical implementation, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
Perform timing closure across multi-corner, multi-mode (MCMM) conditions, ensuring compliance with performance, power, and area (PPA) goals.
Conduct static timing analysis (STA) using PrimeTime or equivalent tools, including timing ECO implementation and signoff validation. ...

Posted

13 days ago

Physical Design Engineer Physical Design Engineer

Alchip Technologies

Undisclosed

Full Time

Bayan Lepas

Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
Perform design IP Implementation, IR drop analysis, DFT, STA and foundry merge.
Work with manager to achieve assigned tape out target. ...

Posted

15 days ago

Physical Design - Lead (PnR-STA) Physical Design - Lead (PnR-STA)

UST

Undisclosed

Full Time

Bayan Lepas

Responsible for Physical Design tasks at block or subsystem level. The tasks will include Floorplanning, Synthesis, Placement, CTS, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.
Owning the entire process from SYN to PNR using Synopsys Fusion Compiler. Crafted the convergence recipe & design collateral to meet project requirement.
Run signoff flow including PV, extraction, STA, VCLP, FEV and EMIR, analyse the violation and converge the design. ...

Posted

15 days ago

IP Design Engineer (RTL) IP Design Engineer (RTL)

Silicon One

Undisclosed

Full Time

Bayan Lepas

Architecture & Protocol Research: Deeply understand company FPGA device architectures, application scenarios, classic algorithms, and protocol specifications.
End-to-End IP Development: Analyze market requirements to define architectures and design algorithm models (C/C++, Matlab, etc.). Write RTL code (Verilog/VHDL), create reference designs, and develop verification environments (SystemVerilog).
IP Packaging & Delivery: Utilize EDA tools and scripts to package IPs, including the development of IP GUIs and comprehensive IP package testing. ...

Posted

18 days ago

IP Design Engineer (RTL - Synthesis) IP Design Engineer (RTL - Synthesis)

Silicon One

Undisclosed

Full Time

Bayan Lepas

IP Design Engineer (RTL & Synthesis)
Location: Bayan Lepas, Penang, Malaysia
Job Type: Full-time (On-site) ...

Posted

21 days ago

Physical Design - Lead (PnR-STA) Physical Design - Lead (PnR-STA)

UST

Undisclosed

Full Time

Bayan Lepas

Responsible for Physical Design tasks at block or subsystem level. The tasks will include Floorplanning, Synthesis, Placement, CTS, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.
Owning the entire process from SYN to PNR using Synopsys Fusion Compiler. Crafted the convergence recipe & design collateral to meet project requirement.
Run signoff flow including PV, extraction, STA, VCLP, FEV and EMIR, analyse the violation and converge the design. ...

Posted

a month ago