Equipment Operation & Maintenance: Proficiently operate ICT testing machines, functional test fixtures, and automated testing equipment. Perform daily inspections and basic preventive maintenance.
Product Testing: Execute testing procedures according to work instructions and accurately determine test results as “Pass” or “Fail.”
Initial Troubleshooting: Conduct preliminary analysis on failed products to identify whether issues are caused by product defects or testing equipment/program problems, and report according to established procedures.
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The candidate will need to perform setup, research, development and test execution of sustaining the TestOps automation for Embedded OS Imaging SQ, driving the transition from manual testing to fully automated operational testing to speed up the entire SQ cycle supporting multiple platforms (PXIe, AXIe, and other instruments).
Responsibilities include development of test strategy, test plan and test cases for device library, BSP & Kernel OS.
Develop test methodology for the planned test and ensure it achieve the testing goal.
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Perform detailed failure analysis on defective materials, components, or products using appropriate analytical tools and techniques to identify root causes and support continuous quality improvement.
Interpret results, monitor failure trends, and implement corrective and preventive actions in collaboration with cross-functional teams to prevent recurrence and improve product reliability.
Follow all laboratory safety protocols and standard operating procedures, maintain accurate documentation and reporting, and ensure proper handover of analysis status and findings between shifts or team members.
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Research and propose alternative parts with effective solutions in consideration of avoiding major software & product calibration, hardware topology changes to replace EOL parts in NI products.
Implement and simulate designs through CAD and synthesis tools. i.e. Mentor Graphics.
Verify and validate designs of hardware re-designs. Debug any issues that may arise.
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Responsible for Physical Design tasks at block or subsystem level. The tasks will include Floorplanning, Synthesis, Placement, CTS, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.
Owning the entire process from SYN to PNR using Synopsys Fusion Compiler. Crafted the convergence recipe & design collateral to meet project requirement.
Run signoff flow including PV, extraction, STA, VCLP, FEV and EMIR, analyse the violation and converge the design.
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