Test Program Architecture & Strategy: Lead the development of comprehensive test strategies from pre-silicon to mass production. Define test flow architecture, including wafer sort, final test, and system-level test (SLT) requirements to ensure high-quality delivery.
Test Program Architecture & Strategy: Lead the development of comprehensive test strategies from pre-silicon to mass production. Define test flow architecture, including wafer sort, final test, and system-level test (SLT) requirements to ensure high-quality delivery.
Test Program Architecture & Strategy: Lead the development of comprehensive test strategies from pre-silicon to mass production. Define test flow architecture, including wafer sort, final test, and system-level test (SLT) requirements to ensure high-quality delivery.
Test Program Architecture & Strategy: Lead the development of comprehensive test strategies from pre-silicon to mass production. Define test flow architecture, including wafer sort, final test, and system-level test (SLT) requirements to ensure high-quality delivery.
Responsible for identifying, analysing OOC lots, Defect Pareto, defect trend and characterization data to determine the source of defect and drive for yield improvement.
Support or lead projects for the adoption of ready S&T or translation of proof-of-concept (POC) or conduct of POC initiatives to deliver systems with view towards operational deployment.
Experience of providing performance test solution for complex architecture of banking solutions involving multiple application in the range of 10-15 applications and also multiple technologies like mainframe, AS 400.
Responsible for ensuring the planning, execution, reporting, and successful completion of QA activities for all new development cycles for various releases.
Responsible for developing, testing, and improving premium connections and OCTG products during the development phase, ensuring they meet rigorous industry standards.
Next-Gen Test Development: Architect and bring up advanced ATE test programs for flagship networking switch ICs featuring high-speed SERDES (>100G) and cutting-edge multi-die CoWoS advanced packaging.
Test Program Architecture & Strategy: Lead the development of comprehensive test strategies from pre-silicon to mass production. Define test flow architecture, including wafer sort, final test, and system-level test (SLT) requirements to ensure high-quality delivery.
Responsible for developing, testing, and improving premium connections and OCTG products during the development phase, ensuring they meet rigorous industry standards.