Establish a foundational framework for Third-Party Security Diligence (3PSD) engineering to automate and integrate security requirements seamlessly into the broader One Third Party Risk Management (TPRM) ecosystem.
Architect AI/ML-driven automation to accelerate vendor on boarding velocity and implement a centralized data engine that provides executive-level visibility and granular risk metrics across Alphabet.
Manage Complex Escalations, act as the primary technical lead for escalations, evaluating edge-case architectures and designing technical road maps for high-risk vendors to ensure they meet Alphabet’s security standards.
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Bachelor / Master’s degree in electrical & Electronic Engineering with at least 3 years of relevant experience in leading successful CMOS IC Test development projects.
• Experience in Advantest 93K tester (should be familiar with SMT 7 & 8) or J750
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Design and build the database and its architecture: the schema, the entities and how they relate, and the structure that turns today's scattered data into one properly organised whole.
Build support for monthly time-series forecast data, scenario versioning, and multi-tenant workspaces with role-scoped access.
Produce a full data dictionary: every field, its type, unit, source, and how it connects to the rest.
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