Vlsi Jobs in Pulau Pinang - August 2026 - Urgent Hiring

Showing 12 jobs results for "vlsi" in Pulau Pinang
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Undisclosed
  • Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
  • Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
  • On time quality delivery approved by the project lead/manager ...
Posted
16 days ago
Undisclosed
Posted
21 days ago
Undisclosed
  • Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
  • Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
  • On time quality delivery approved by the project lead/manager ...
Posted
a month ago
Undisclosed
  • Custom Layout Engineer
  • Bayan Lepas, Penang
  • Location: Bayan Lepas, Penang, Malaysia ...
Posted
8 days ago
Undisclosed

George Town

  • 3–12 years of hands-on IC Custom Layout experience, with the ability to work independently or lead layout planning.
  • Strong experience with TSMC process nodes, preferably advanced FinFET technologies (7nm, 5nm, or 3nm).
  • Proven experience in custom Analog and High-Speed Mixed-Signal layout, including HSIO, SerDes (TX/RX), PLLs, VCOs, and Bandgap circuits. ...
Posted
9 days ago
Undisclosed
  • Reliability Analysis (EMIR): Perform rigorous Electromigration (EM) and IR Drop analysis to ensure long-term reliability and power integrity of high-current density paths.
  • Physical Verification: Execute and resolve complex DRC, LVS, ERC, and Antenna violations to ensure 100% tape-out readiness.
  • Block-Level Execution: Lead high-quality custom layout for various blocks, including SerDes (TX/RX), PLL, ESD, Mixed-Signal IO, and Digital Blocks. ...
Posted
16 days ago
Undisclosed

Malaysia

  • Lead and oversee semiconductor design activities in:
  • Physical Design (PnR, STA, Signoff) or
  • Design Verification (RTL/GLS, UVM, coverage-driven verification) ...
Posted
17 days ago
Undisclosed

Malaysia

  • End-to-end physical design: Floorplan, PnR, CTS, routing
  • Drive timing closure using STA (MCMM analysis)
  • Fix setup/hold violations and optimize PPA (power, performance, area) ...
Posted
9 days ago
Undisclosed

Malaysia

  • THE ROLE:
  • We are seeking an adaptive, self-motivated Physical Design Engineer to join our growing team. As a key contributor, you will help drive AMD’s capabilities in delivering high-performance, power-efficient silicon solutions. The Physical Design team values continuous technical innovation and supports professional growth through challenging projects and collaborative success. In this role, you will be responsible for full-chip floorplanning, physical implementation, timing closure, and power optimization across complex SoC designs.
  • THE PERSON: ...
Posted
9 days ago
Undisclosed
  • Custom Layout Engineer
  • Bayan Lepas, Penang
  • Location: Bayan Lepas, Penang, Malaysia ...
Posted
21 days ago
Undisclosed
  • Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
  • Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning, layout construction, physical verification and QA flow sign-off.
  • Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project. ...
Posted
23 days ago
Undisclosed

Malaysia

  • Lead RTL design and implementation for AI chip SoC and subsystems.
  • Own key modules such as AI accelerator control logic, DMA, NoC/interconnect, memory subsystem, die-to-die/chip-to-chip interfaces, register blocks, interrupt, clock/reset, and low-power control.
  • Define microarchitecture, RTL partitioning, interfaces, and implementation plans. ...
Posted
21 days ago

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