Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
On time quality delivery approved by the project lead/manager
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Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
On time quality delivery approved by the project lead/manager
...
Reliability Analysis (EMIR): Perform rigorous Electromigration (EM) and IR Drop analysis to ensure long-term reliability and power integrity of high-current density paths.
Physical Verification: Execute and resolve complex DRC, LVS, ERC, and Antenna violations to ensure 100% tape-out readiness.
Block-Level Execution: Lead high-quality custom layout for various blocks, including SerDes (TX/RX), PLL, ESD, Mixed-Signal IO, and Digital Blocks.
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We are seeking an adaptive, self-motivated Physical Design Engineer to join our growing team. As a key contributor, you will help drive AMD’s capabilities in delivering high-performance, power-efficient silicon solutions. The Physical Design team values continuous technical innovation and supports professional growth through challenging projects and collaborative success. In this role, you will be responsible for full-chip floorplanning, physical implementation, timing closure, and power optimization across complex SoC designs.
Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning, layout construction, physical verification and QA flow sign-off.
Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project.
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Lead RTL design and implementation for AI chip SoC and subsystems.
Own key modules such as AI accelerator control logic, DMA, NoC/interconnect, memory subsystem, die-to-die/chip-to-chip interfaces, register blocks, interrupt, clock/reset, and low-power control.
Define microarchitecture, RTL partitioning, interfaces, and implementation plans.
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