- Bayan Lepas Pulau Pinang Malaysia
Kerja Sepenuh Masa, Engineering Technical Lead di AdoreSys Pulau Pinang - Maukerja
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Position: R&D Engineering Lead (Custom IC Layout)
Overview:
Are you passionate about driving innovation in microchip design? Are you ready to take the lead in shaping the next generation of integrated circuits? We’re seeking an experienced R&D Engineering Lead for Custom IC Layout operation. The established team will undertake custom layout implementation using advanced CMOS technology for our next-generation SoCs – including the chips powering tomorrow’s AI breakthroughs.
What you’ll do:
Lead and manage a team of custom layout engineers in undertaking custom IC layout tasks for Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP and RF building blocks, using advanced CMOS process nodes across multiple foundries.
Participate in recruitment and team development activities, including candidate interviews, new hire orientation, performance assessment, technical coaching, conflict resolution and team capability building.
Be responsible for the project management of the assigned tasks, including but not limited to schedule planning, resource allocation, project tracking and reporting, issue debugging and resolution and QA/QC signoff.
Serve as the primary point of contact across multiple functional teams or customers, driving project-specific KPIs and ensuring timely delivery through effective risk mitigation strategies.
Who we’re looking for:
Bachelor’s or Master’s degree in EE/EEE, CE/CS, or a related technical discipline.
More than 12 years of relevant semiconductor industry experience in custom IC layout, backend physical implementation, or related IC design implementation roles.
Proven experience leading layout engineering teams, contractor teams, outsourced design teams, or cross-site engineering organizations.
Strong hands-on background in custom IC layout implementation using advanced CMOS technologies.
Proficiency with industry-standard EDA tools (Cadence, Synopsys, and Siemens) as well as layout automation.
Deep technical understanding of layout requirements for one or more of the following domains: Standard Cells, Memory Compilers, IO/ESD Pads, Analog/RF IP and Digital APR.
Strong analytical and problem-solving capability, with the ability to debug complex layout, verification, methodology, and implementation issues.
Self-motivated, proactive, and committed to continuous improvement in engineering quality, team productivity, and methodology efficiency.
If you are an experienced IC layout leader with a strong background in advanced CMOS implementation, custom layout methodology, and engineering team management, we invite you to join us in developing the next generation of high-performance SoCs powering future AI and computing applications.
Overview:
Are you passionate about driving innovation in microchip design? Are you ready to take the lead in shaping the next generation of integrated circuits? We’re seeking an experienced R&D Engineering Lead for Custom IC Layout operation. The established team will undertake custom layout implementation using advanced CMOS technology for our next-generation SoCs – including the chips powering tomorrow’s AI breakthroughs.
What you’ll do:
Lead and manage a team of custom layout engineers in undertaking custom IC layout tasks for Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP and RF building blocks, using advanced CMOS process nodes across multiple foundries.
Participate in recruitment and team development activities, including candidate interviews, new hire orientation, performance assessment, technical coaching, conflict resolution and team capability building.
Be responsible for the project management of the assigned tasks, including but not limited to schedule planning, resource allocation, project tracking and reporting, issue debugging and resolution and QA/QC signoff.
Serve as the primary point of contact across multiple functional teams or customers, driving project-specific KPIs and ensuring timely delivery through effective risk mitigation strategies.
Who we’re looking for:
Bachelor’s or Master’s degree in EE/EEE, CE/CS, or a related technical discipline.
More than 12 years of relevant semiconductor industry experience in custom IC layout, backend physical implementation, or related IC design implementation roles.
Proven experience leading layout engineering teams, contractor teams, outsourced design teams, or cross-site engineering organizations.
Strong hands-on background in custom IC layout implementation using advanced CMOS technologies.
Proficiency with industry-standard EDA tools (Cadence, Synopsys, and Siemens) as well as layout automation.
Deep technical understanding of layout requirements for one or more of the following domains: Standard Cells, Memory Compilers, IO/ESD Pads, Analog/RF IP and Digital APR.
Strong analytical and problem-solving capability, with the ability to debug complex layout, verification, methodology, and implementation issues.
Self-motivated, proactive, and committed to continuous improvement in engineering quality, team productivity, and methodology efficiency.
If you are an experienced IC layout leader with a strong background in advanced CMOS implementation, custom layout methodology, and engineering team management, we invite you to join us in developing the next generation of high-performance SoCs powering future AI and computing applications.
Peringatan Penting
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