Kerja Sepenuh Masa, ASIC Graduate Engineer di AdoreSys Pulau Pinang - Maukerja

Job Descriptions:

• Design and develop RTL code (Verilog/SystemVerilog) for digital logic blocks and SoC subsystems
• Perform functional verification including testbench development, simulation, and coverage-driven verification using industry-standard methodologies (UVM)
• Conduct static timing analysis (STA) to meet timing targets across PVT corners, and work on timing closure through constraint tuning and ECO
• Support physical design activities including floorplanning, place and route, and congestion resolution in collaboration with the backend team

Requirements:

• Bachelor's degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Microelectronics, or a related field
• Basic knowledge of digital IC design
• Knowledge of Verilog/System Verilog and UVM
• Knowledge of scripting languages (Python, Tcl, Perl, or Shell) is a plus
• Good problem-solving, communication, and teamwork skills
• Willingness to learn and grow in the semiconductor industry