Design For Test Engineer - DFT
Employment type : Open to Perm & Contract
Working arrangement : Onsite
Location: Bayan Lepas, Penang
Salary Range : 4 – 6 Years (11-12k), 6 – 8 Years (13-15k), 8 – 10 Years (16-18k)
Position Overview
We are seeking an experienced Design-for-Test (DFT) Engineer to develop and implement DFT solutions for high-performance ASICs and SoCs. The role focuses on delivering high manufacturing test coverage, optimized test cost, and efficient test execution while maintaining power, performance, and area (PPA) targets.
Key Responsibilities
- Define and implement chip-level DFT architecture, including scan, MBIST, LBIST, JTAG, IJTAG, and IEEE 1500 wrapper chains.
- Develop test strategies, clock/reset architectures, and DFT specifications for complex SoCs.
- Integrate scan compression solutions using industry-standard EDA tools (Synopsys DFTMAX, Siemens Tessent, Cadence Modus).
- Generate and optimize ATPG patterns for Stuck-at, Transition Delay, Cell-Aware, and Path Delay fault models.
- Verify DFT implementation through RTL and gate-level simulations, and perform pre- and post-layout DFT validation.
- Support silicon bring-up, ATE debugging, failure analysis, and yield improvement in collaboration with product engineering teams.
- Develop automation scripts using Tcl, Python, or Perl to improve DFT flow efficiency.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
- 4–15 years of hands-on experience in ASIC/SoC DFT implementation.
- Strong knowledge of Verilog/SystemVerilog/VHDL, digital design, and synthesis.
- Hands-on experience with Synopsys (Design Compiler, DFTMAX, TetraMAX, Fusion Compiler), Siemens Tessent/FastScan/TestKompress, or Cadence Modus/Genus.
- Proficiency in Tcl, Python, or Perl scripting for automation.
- Experience with production DFT flows, ATPG, scan insertion, MBIST/LBIST, and silicon debug is highly preferred.
If you are interested, please send your updated resume to ************* OR WA to +*************