Kerja Sepenuh Masa, Senior Physical Design Engineer di Avecas Pulau Pinang - Maukerja

Company Description Avecas is a global technology and engineering services company focused on semiconductor, VLSI design, embedded systems, and silicon product engineering. The company partners with innovators across the USA, Europe, the UK, and Asia to accelerate development of next-generation chips and intelligent systems. Avecas delivers end-to-end engineering services from concept and architecture through design, implementation, validation, tapeout, and production support for advanced nodes and complex SoCs. Its teams specialize in RTL design, verification, physical design, DFT, power and reliability, signoff, embedded software, and system integration for industries such as automotive, AI, networking, telecom, consumer electronics, and industrial automation. Avecas emphasizes engineering excellence, customer success, and long-term partnerships, working as an extension of customer teams to build scalable, future-ready technology platforms.

Role Description The Senior Physical Design Engineer is a full-time, on-site role based in Bayan Lepas. This role is responsible for driving block- and top-level physical design activities, including floorplanning, partitioning, placement, clock tree synthesis, routing, and timing closure for complex SoCs. The engineer collaborates closely with RTL, logic design, DFT, and verification teams to ensure clean handoff, robust implementation, and signoff-quality results across PPA (power, performance, area) metrics. Daily tasks include running and analyzing static timing, power and IR drop, EM checks, and physical verification, as well as debugging issues related to congestion, timing, noise, and design rules. The role also involves preparing implementation and signoff reports, contributing to flow and methodology improvements, and mentoring junior engineers to ensure high-quality delivery aligned with customer schedules.

Qualifications

• Strong skills in Physical Design, including floorplanning, placement, CTS, routing, and timing closure for complex SoCs.
• Proficiency in Physical Verification, covering DRC, LVS, antenna checks, and reliability signoff at advanced technology nodes.
• Solid foundation in Logic Design and Circuit Design, with understanding of digital design fundamentals, clocking, and low-power techniques.
• Experience with RTL Design environments and interfaces, enabling effective collaboration with front-end teams for implementation and ECOs.
• Hands-on experience with industry-standard EDA tools (e.g., Cadence, Synopsys, Siemens) for implementation, STA, power analysis, and signoff.
• Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or a related technical field.
• Demonstrated ability to lead complex blocks or top-level designs, manage schedules, and work effectively with cross-functional global teams.
• Strong problem-solving skills, attention to detail,