Kerja Sepenuh Masa, Physical Design Senior Engineer di SIGNOFF SEMICONDUCTORS PVT. LTD. Pulau Pinang - Maukerja

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time

Bayan Lepas, Malaysia | Posted on 06/17/2026

SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

• Lead and own the physical design flow from RTL - GDSII for complex blocks.
• Drive floorplanning, power planning, placement, clock tree synthesis (CTS), routing and signoff (timing, IR, EM, DRC/LVS).
• Handle complex blocks including multiple blocks if required.
• Interact with sub-system leads and full-chip owner to provide necessary feedback.
• Analyze and optimize PPA (Power, Performance, Area) to meet design targets.
• Collaborate with RTL, STA, power DFT and verification for design convergence.
• Lead ECO cycles for timing, congestion and physical signoff closure.
• Review and debug physical verification and timing issues.
• Manage schedules, and risk tracking for PD deliverables.
• Prepare and present project status, risk and mitigation plans to sub-system leads and customer.
• Work effectively with large teams consisting of multiple vendors.

• 6-9 years of experience in ASIC/SOC Physical Design handling complex blocks.
• Strong expertise in industry standard PD tools (Innovus, Tempus, Voltus, RedHawk, Calibre).
• Proven experience in block closure and signoff flows.
• Good understanding of STA, Physical Verification and low-power design methodologies (UPF/CPF).
• Hands on experience with lower process nodes (16nm and below preferred).
• Strong debugging and problem solving skills in timing, congestion and physical verification.
• Hands on experience in handling Analog custom routes, understanding specification to meet R and C.
• Experience in multi-voltage, multi-frequency design.
• Knowledge of EM/IR-drop analysis and mitigation.
• Excellent communication and leadership skills.