Full Time Senior Package Design Engineer (Cadence APD Layout) Jobs, in UST Pulau Pinang - Maukerja

We are looking for a Senior Package Design Engineer with deep hands-on expertise in Cadence Allegro Package Designer (APD) to join us on a contract basis. This is a layout-focused role. You will personally execute substrate layout from netlist import through routing, DRC clean-up, and tape-out release for flip-chip and wire-bond packages. You will work closely with silicon design, SI/PI, thermal, and substrate vendor teams to deliver packages that meet electrical, mechanical, and manufacturing targets.

Key Responsibilities

· Perform end-to-end substrate layout in Cadence APD, including library and footprint setup, die placement, stackup and constraint setup, routing, plane and shape creation, and final release.

· Route high-speed and high-density interfaces (DDR/LPDDR, PCIe, SerDes, MIPI, USB) in APD, applying length matching, differential pair, impedance, and spacing constraints through the Constraint Manager.

· Design robust power and ground distribution, including plane and shape strategy, via arrays, and decoupling capacitor placement.

· Define stackup and design rules with substrate vendors, and ensure designs meet vendor DFM and manufacturing capabilities.

· Run DRC, connectivity, and manufacturing sign-off checks, and generate Gerber/ODB++, drawings, and release packages.

· Work with SI/PI and thermal engineers to close electrical and thermal requirements, and implement layout changes from their feedback.

· Support design reviews with OSAT and substrate suppliers, and resolve engineering queries during prototype and production builds.

Required Qualifications

· At least 8 years of hands-on semiconductor package layout experience, with a minimum of 5 years of daily production use of Cadence APD.

· Proven, strong APD layout skills, shown by multiple packages taken from netlist to tape-out. Candidates should be able to discuss their layout work in detail and demonstrate it in a technical interview or layout exercise.

· Expert knowledge of APD features, including Constraint Manager, shape and plane editing, bond finger and wire bond tools, die stacking, and DRC and manufacturing outputs.

· Experience laying out flip-chip and/or wire-bond packages (FCBGA, FCCSP, WLCSP, BGA/LGA) on organic substrates.

· Solid understanding of substrate build-up stackups, via structures, fine-line routing limits, and vendor design rules.

· Experience routing high-speed interfaces and high-current power delivery.

· Ability to work independently, meet tight schedules, and deliver clean, manufacturable layouts with minimal rework.

· Good written and verbal communication skills in English.

Preferred Qualifications

· Experience with APD+, Allegro SiP Layout.

· Direct working experience with OSATs and substrate vendors, and support for package qualification.

· Track record of packages released to high-volume production.