Design and Development: Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM)
Architecture and Implementation: Develop memory architectures and implement them in advanced semiconductor technologies, including FinFET and nanometer CMOS
Simulation and Verification: Perform schematic capture, simulation, and margin verification of major memory blocks
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Design and Development: Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM)
Architecture and Implementation: Develop memory architectures and implement them in advanced semiconductor technologies, including FinFET and nanometer CMOS
Simulation and Verification: Perform schematic capture, simulation, and margin verification of major memory blocks
...
Design and Development: Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM)
Architecture and Implementation: Develop memory architectures and implement them in advanced semiconductor technologies, including FinFET and nanometer CMOS
Simulation and Verification: Perform schematic capture, simulation, and margin verification of major memory blocks
...
Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
On time quality delivery approved by the project lead/manager
...
Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
On time quality delivery approved by the project lead/manager
...
Responsible for Physical Design tasks at block or subsystem level. The tasks will include Floorplanning, Synthesis, Placement, CTS, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.
Owning the entire process from SYN to PNR using Synopsys Fusion Compiler. Crafted the convergence recipe & design collateral to meet project requirement.
Run signoff flow including PV, extraction, STA, VCLP, FEV and EMIR, analyse the violation and converge the design.
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Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
On time quality delivery approved by the project lead/manager
...
Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
On time quality delivery approved by the project lead/manager
...