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D&I Statement
As an equal-opportunity employer, Nexperia values diversity not just because it is the right thing to do but because diverse teams perform better. We are dedicated to being inclusive, and a proof point of this dedication is that we were the main partner of the very first Dutch Paralympic Team NL House during the Paris 2024 Paralympic Games. Our recruitment process is inclusive and accessible to all, and we consider all applicants fairly, as well as providing a safe work environment and reasonable adjustments where requested.
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Lead maintenance, optimization, and continuous improvement of trim and form equipment across multiple semiconductor package types.
Monitor equipment downtime (DT) and develop mitigation strategies using MTBF/MTBA analysis; regularly assess the effectiveness of scheduled downtime activities and ensure proper verification and buy-off.
Partner with Process Engineering during new product development and qualification to ensure trim and form equipment readiness for high-volume manufacturing (HVM).
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Lead maintenance, optimization, and continuous improvement of trim and form equipment across multiple semiconductor package types.
Monitor equipment downtime (DT) and develop mitigation strategies using MTBF/MTBA analysis; regularly assess the effectiveness of scheduled downtime activities and ensure proper verification and buy-off.
Partner with Process Engineering during new product development and qualification to ensure trim and form equipment readiness for high-volume manufacturing (HVM).
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The purpose of this position is to ensure effective quality management and continuous improvement for Seremban Load & Haul operations by leading quality issue handling, root cause analysis, corrective and preventive actions and Quality Management System compliance. The Quality Engineer works closely with production, warehouse, planning, logistics, supplier quality, engineering, and other relevant stakeholders to investigate quality concerns, prevent recurrence of non-conformities, improve process capability, support customer and internal quality requirements, and ensure products are delivered in accordance with Sandvik quality standards, ISO 9001 requirements, and applicable procedures.
PRIMARY AREAS OF RESPONSIBILITY
· Lead quality feedback analysis by reviewing defect information, identifying trends, verifying root causes, coordinating containment actions, and ensuring timely follow-up and closure of quality issues.
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Lead maintenance, optimization, and continuous improvement of trim and form equipment across multiple semiconductor package types.
Monitor equipment downtime (DT) and develop mitigation strategies using MTBF/MTBA analysis; regularly assess the effectiveness of scheduled downtime activities and ensure proper verification and buy-off.
Partner with Process Engineering during new product development and qualification to ensure trim and form equipment readiness for high-volume manufacturing (HVM).
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Support daily routine works as specified in the key responsibilities of QA/QC Engineer.
Responsible for highlighting & noncompliance documentation on material, processes , products, environment & methodologies compliance to specifications or standards. Responsible for highlighting & noncompliance documentation on procedural inadequacy.
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Support daily routine works as specified in the key responsibilities of QA/QC Engineer.
Responsible for highlighting & noncompliance documentation on material, processes , products, environment & methodologies compliance to specifications or standards. Responsible for highlighting & noncompliance documentation on procedural inadequacy.
Good understanding in local applicable laws, any regulations or procedures, standards/codes and ensure compliance in the work area. Encourage workers and or to report any kind of violations relating to labour, ethics and EHS.
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Perform general and specific preventive and corrective maintenance on semiconductor manufacturing equipment. Requires the use of diagnostic equipment and procedures to maintain and repair production equipment. Majority of work is conducted in a cleanroom environment requiring the wearing of specific clothing to be worn over regular clothing.
Participate in continuous improvement activities.
Participate as part of a team or independently in identifying and solving problems
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As a Senior Failure Analysis Engineer, you will play a key role in identifying and determining the root causes of semiconductor device failures. You will perform comprehensive failure analysis at the wafer, package, and die levels, working closely with cross-functional engineering teams to support product quality, reliability, and continuous improvement. This position requires strong technical expertise in failure analysis techniques, electrical fault isolation, and semiconductor manufacturing processes.
Perform failure analysis (FA) on wafer, package, and die-level semiconductor devices, including electrical verification, fault isolation, and physical root cause analysis.
Prepare detailed FA reports with clear findings and recommendations to support corrective and preventive actions.
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