FPGA-RTL Design Engineer (High Speed Ethernet)UST MalaysiaUndisclosedView SalaryFull TimeBayan LepasProficiency with HDL design such as Verilog, System Verilog, and VHDL.12 daysSaveApply Now
ASIC Front-End Integration Engineer (RTL, Synthesis, CDC, LEC, UPF)UST MalaysiaUndisclosedView SalaryFull TimeBayan Lepas26 daysSaveApply Now