To lead technically in ASIC physical design domain, which may include stages from design specification understanding till layout and timing signoff for tapeout
To develop and signoff I.C. design projects physical design and flow improvement. Responsibilities include (as applicable)
Effective and efficient auto Place-and-Route implementation, covering floorplanning, PG mesh, placement, CTS, routing and chip-finishing
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Bachelors, Masters or better in Computer Science, Computer Engineering, Electrical Engineering, or related fields with 8+ years of experience in SoC and/or FPGA IP development.
Strong communication skills.
Knowledge or experience in FPGA architecture and FPGA software tools, specifically for device modeling and soft IP development.
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