WD thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Responsible for the circuit design, simulation, and verification of key analog/mixed-signal modules for 3D-NAND memory, including but not limited to: 1) XDec/Page buffer/Datapath design and optimization. 2) High-Voltage (HV) Charge Pump/PUMP architecture design to meet multi-voltage domain, high efficiency, and low noise requirements. 3) High-voltage switch (HV Switch) and HV level shifter design to support >20V high-voltage operation. 4) I/O interface circuitry (including ESD protection, drive capability matching, and signal integrity optimization).
Establish and maintain Verilog-A behavioral models of key modules for rapid system-level simulation and verification;
Perform array-level mixed-mode simulation, proficient in using tools such as SPICE, Spectre, and HSPICE, and combining Verilog/Verilog-AMS for large-scale circuit verification;
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At Alcon, we are driven by the meaningful work we do to help people see brilliantly. We innovate boldly, champion progress, and act with speed as the global leader in eye care. Here, you’ll be recognized for your commitment and contributions and see your career like never before. Together, we go above and beyond to make an impact in the lives of our patients and customers. We foster an inclusive culture and are looking for diverse, talented people to join Alcon.
ATTENTION: Current Alcon Employee/Contingent Worker
Research and propose alternative parts with effective solutions in consideration of avoiding major software & product calibration, hardware topology changes to replace EOL parts in NI products.
Implement and simulate designs through CAD and synthesis tools. i.e. Mentor Graphics.
Verify and validate designs of hardware re-designs. Debug any issues that may arise.
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Subject matter expert (SME) for laboratory testing asset lifecycle:
Manage and maintain laboratory testing asset (LTA) lifecycle, including selection, procurement, qualification, periodic review, re-qualification and decommissioning of LTA.
Develop protocols/procedures, execute qualification and implementation of laboratory testing assets and systems, and prepare reports accordingly within project timeline and budget. Coordinate and complete change requests.
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Use industry standard electrical design tools to design, simulate, and verify board level analog circuits for test and measurement applications, including: Linear power supplies
Switched mode power supplies (DC–DC)
High precision/highspeed analog front ends (including ADCs, DACs, amplifiers)
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Process integration development for high density multi-chip fan-out wafer level packaging for various applications such as AI/ HPC, Co-package Optics, Power devices etc.
Drive the development of new capabilities such as fine pitch RDL, micro bumping, multi-layer RDL, polymer damascene etc required for future FOWLP integration.
Establish novel RDL-first and mold-first fan-out packaging integration flows to meet industry partners requirements for various applications.
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