Physical Design Engineer
- Carry out backend IC design physical implementation work (aka PNR) for advanced SoC/ASIC designs from SYN to GDS.
7 days
1,100+ IT Quality Assurance Jobs - November 2026 - Urgent Hiring - Page 31
Showing 1,173 jobs results for
"it quality assurance"
(Sr.-Staff) ASIC Design Engineer
- Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection.
7 days
Semiconductor Test Technician
- Executeevaluation for test program or product qualification activities.
7 days
Engineer (IC Design)
- Perform full-chip IC physical design development of products for FTDI products
7 days
7 days
Physical Verification Sign-off, Technical Manager
- Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT,ERC, ESD, PERC) fortape-out.
7 days
Engineer-Staff Engineer – Multi-Dies Physical Verification Engineer
- Responsible for Multi-Dies Physical Verification Sign-off in area of (3D_Stack, 3D_PERC, 3D_ANT) for tape-out.
7 days
- IC physical design of 12nm/6nm/4nm and below world leading advanced process chip, from RTL to GDS.
7 days
Assoc Specialist, QA
- Work for a global leader in the health and safety protection solutions industry.
30+ days
Assembly Operator (Data Centre) | $2800 - $3500 | 4 Days Work Week | Tampines
- Assemble servers, chassis, hard drives, and related components
8 days
IC Verification Engineer
- Develop and execute comprehensive verification plans at IP and SoC levels.
8 days
Sr- IC Design Engineer (Physical Design)
- Design and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing.
8 days
Sr- IC Design Engineer (Design Verification)
- Develop and Review Test Plan based on IC design specification
8 days
Senior- IC Design Engineer (Design Verification)
- Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications.
8 days
DFT Engineer
- DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST
8 days
QS Manager ( ID Fit Out)
- To lead and supervise the contract team for daily contractual matters.
27 days
IC Layout Engineer
- Layout Design & Execution: Apply design guidelines and advanced process rules to deliver high-performance, robust layouts.
8 days
Senior Packaging Development Engineer - Substrate Modules
- Optimizing and establishing robust and high-speed process parameters for various component attach processes, stack-up, and molding (transfer or compression) technology
8 days
DFT Engineer
- Develop efficient and cost-effective structural and functional test patterns to ensure product quality and meet release schedules.
9 days
Semiconductor Test Engineer (Advantest V93K-Teradyne UFLEX)
- Develop and debug ATE test programs for Digital, PMIC, RF, and Mixed-Signal semiconductor products using Advantest V93000 (SmartTest 7/8) and/or Teradyne UFLEX platforms.
9 days
9 days
Semiconductor Test Engineer (Advantest V93K-Teradyne UFLEX)
- Develop and debug ATE test programs for Digital, PMIC, RF, and Mixed-Signal semiconductor products using Advantest V93000 (SmartTest 7/8) and/or Teradyne UFLEX platforms.
10 days
Senior IT Business Analyst [Min 5 years of experience required]
29 days
- Responsible for physical design and development of a variety of SoCs (System on Chip) and tapeout.
10 days
Quality Executive (II)
- Support the implementation, maintenance, and continual improvement of the Integrated Management System (IMS) covering ISO 9001, ISO 41001, ISO 22301, and ISO 27001.
30+ days
Semiconductor Test Engineer (Advantest V93K-Teradyne UFLEX)
- Develop and debug ATE test programs for Digital, PMIC, RF, and Mixed-Signal semiconductor products using Advantest V93000 (SmartTest 7/8) and/or Teradyne UFLEX platforms.
11 days
- Responsible for Full-chip Physical Verification Sign-off in area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
11 days
- Define ADC and analog subsystem specifications and architectures.
11 days
Scientist (IC Designer), IME
- Develop AI-based circuit design and optimization flows using LLMs, machine learning, optimization algorithms, and Cadence EDA tools.
12 days
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