Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
Lead the Extra-Low Voltage systems design on assigned large scale projects during the tender, design, procurement, construction, commissioning until finale client acceptance phase
Develop and debug ATE test programs for Digital, PMIC, RF, and Mixed-Signal semiconductor products using Advantest V93000 (SmartTest 7/8) and/or Teradyne UFLEX platforms.
Support LIMS masterdata update and improvement projects (site & global), including LIMS change assessment and liaise with global personnel for the change implementation