DFT Engineer
- DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST
10 days
3,200+ QA Engineer Jobs in Malaysia | Job Vacancies | November 2026 | Maukerja - Page 94
Showing 3,207 jobs results for
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IC Layout Engineer
- Layout Design & Execution: Apply design guidelines and advanced process rules to deliver high-performance, robust layouts.
10 days
Desktop Assistant - PC Builder
10 days
Senior Packaging Development Engineer - Substrate Modules
- Optimizing and establishing robust and high-speed process parameters for various component attach processes, stack-up, and molding (transfer or compression) technology
10 days
Desktop Assistant - PC Builder
- Understand the company structure, brand and work environment in the IT sector
10 days
DFT Engineer
- Develop efficient and cost-effective structural and functional test patterns to ensure product quality and meet release schedules.
11 days
Semiconductor Test Engineer (Advantest V93K-Teradyne UFLEX)
- Develop and debug ATE test programs for Digital, PMIC, RF, and Mixed-Signal semiconductor products using Advantest V93000 (SmartTest 7/8) and/or Teradyne UFLEX platforms.
11 days
Semiconductor Test Engineer (Advantest V93K-Teradyne UFLEX)
- Develop and debug ATE test programs for Digital, PMIC, RF, and Mixed-Signal semiconductor products using Advantest V93000 (SmartTest 7/8) and/or Teradyne UFLEX platforms.
12 days
- Learn to troubleshoot, repair and replace faulty components within a server.
12 days
Semiconductor Test Engineer (Advantest V93K-Teradyne UFLEX)
- Develop and debug ATE test programs for Digital, PMIC, RF, and Mixed-Signal semiconductor products using Advantest V93000 (SmartTest 7/8) and/or Teradyne UFLEX platforms.
13 days
- Responsible for Full-chip Physical Verification Sign-off in area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
13 days
IT DEBUG TECHNICIAN
- B: 7pm-7am (Sun – Wed),rest 3 days, (Sun – Tues), rest 4 days, repeat ($336 Shift Allowance)
13 days
- Learn to troubleshoot, repair and replace faulty components within a server.
13 days
Scientist (IC Designer), IME
- Develop AI-based circuit design and optimization flows using LLMs, machine learning, optimization algorithms, and Cadence EDA tools.
14 days
Testing - Commissioning (T-C) Engineer
- Plan, coordinate and execute testing and commissioning activities in accordance with approved procedures, project specifications and commissioning plans.
23 days
Physical Design Engineer
- Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
14 days
DFT Engineer
- Develop efficient and cost-effective structural and functional test patterns to ensure product quality and meet release schedules.
15 days
- Coordinate and execute the tape out process for semiconductor products, ensuring timely and accurate delivery of design data to manufacturing.
15 days
IC CAD engineer
- Own and support Physical Verification (DRC/LVS/ERC) and Parasitic Extraction (PEX) flows in a custom layout environment
23 days
Senior IC Validation Engineer (Electrical Transceiver)
- Debug and resolve silicon issues
15 days
R - Technician
- Visit customer locations to diagnose and troubleshoot product issues.
15 days
15 days
Senior Engineer I-C
- Lead the Extra-Low Voltage systems design on assigned large scale projects during the tender, design, procurement, construction, commissioning until finale client acceptance phase
16 days
(Sr.) Tape Out Engineer
- Coordinate and execute the tape out process for semiconductor products, ensuring timely and accurate delivery of design data to manufacturing.
16 days
Packaging development engineer
- Take ownership of FC-FE die attach and underfill processes for semiconductor packages, including advanced package platforms.
16 days
Test Engineer | Singaporean Only !
30+ days
CSA Package Lead (Semiconductor - Industrial - Science) - Johor
17 days
CSA Package Lead (Semiconductor - Industrial - Science) - Johor
- Manage and oversee all Civil, Structural, and Architectural package activities from design through construction and handover.
17 days
DFT Engineer
- Define and implement chip-level DFT architecture, including scan, MBIST, LBIST, JTAG, IJTAG, and IEEE 1500 wrapper chains.
18 days