Design and development of the test automation framework, considering scalability, performance, and maintainability.
Collaborate with a diverse team of developers, testers, users, and project managers to gather requirements and define architectural solutions that align with the needs of the framework community.
Develop and maintain technical documentation, including architectural diagrams, design patterns, and guidelines for extension and customization.
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Design and development of the test automation framework, considering scalability, performance, and maintainability.
Collaborate with a diverse team of developers, testers, users, and project managers to gather requirements and define architectural solutions that align with the needs of the framework community.
Develop and maintain technical documentation, including architectural diagrams, design patterns, and guidelines for extension and customization.
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Design, develop, train, and evaluate machine learning and deep learning models, including CNNs, Transformers, Diffusion Models, and other Generative AI architectures.
Research, prototype, and implement state-of-the-art AI algorithms, architectures, and training methodologies.
Conduct experiments, benchmark performance, and optimize models for accuracy, efficiency, scalability, and deployment requirements.
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Regularly leads important projects that require providing experienced project team members with instruction, guidance, and advice in all aspects of the project to ensure delivery of quality outcomes.
Responsible for developing & reviewing project member software for automation machines to ensure requirement, functionality & expectation are fully covered.
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Own the architecture, development, and lifecycle of device drivers for on‑chip and external peripherals (Ethernet, PCIe, USB, SPI, I2C, UART, GPIO), ensuring scalability across silicon revisions and product generations.
Design and implement low‑level driver software across bootloader, OS/RTOS, and embedded Linux environments, defining clear driver interfaces aligned with platform‑level software architecture.
Lead system bring‑up and early silicon debug at the HW/SW boundary, resolving complex integration issues using tools such as JTAG and logic analyzers.
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