- Clementi West Region (Singapore) Singapore
Kerja Sepenuh Masa Standard Cell Library Engineer, Gaji tinggi SGD 9,500 di PERSOL West Region (Singapore) - Maukerja
Standard Cell Library Engineer
PERSOL
Kongsi
Simpan
Lokasi Kerja
Penerangan Kerja
Tanggungjawab
You will be in a energetic team working on advanced technology development, as the pioneer to setup leading edge design platform for MediaTek multi-vertical projects.
Develop complex circuit block, test key for leading-edge process node (planar, finfet, nanosheet) from schematic netlist to gds.
Develop standard cell library from architecture evaluation, PPA assessment and customized cell design with different PPA purpose and IP blocks.
Work with layout engineer for design implementation and physical verification including DRC/LVS/ERC/ANT.
Perform layout extraction, simulation, analyze simulation data, including performance, power, leakage, for layout dependent effect study.
Work with digital team and testing team for design implementation and chip level silicon data collection.
Develop processing flow for silicon data analysis, visualization, AI model regression.
Develop advanced library generation methodology and flow, including characterization, kit generation, regression, and quality assurance.
Perform timing/power/constraint/noise/LVF variation characterization for standard cell or complex circuit blocks.
Work with circuit designer and tool vendors to tackle modelling difficulties, like accuracy and runtime issues, especially for complex circuit blocks.
Responsible for new kits enablement and evaluation, like EM characterization, aging characterization.
Involve with data analysis and machine learning as well for circuit performance and power assessment.
Requirement:
Bachelor / Master’s Degree in Electrical and Electronic Engineering/Computer Engineering/Computer Science
Familiar with Python, Perl, Tcl or C/C++ for flow development and data analysis, machine learning.
Basic knowledge of digital design and/or circuit design.
Solid understanding of foundation IP design, with device physics, transistor level circuit, layout dependent effect knowledge.
Experience of test chip design in FinFet/Nanosheet technologies is a plus, with understanding of DRM, layout rules, PV check, and simulation skills.
Strong communication and teamwork skills to collaborate effectively with cross-functional teams.
Interested candidates may apply through the application system. We regret that only shortlisted candidates will be notified.
PERSOL Singapore Pte Ltd • UEN No. 200007268E • EA License No. 01C4394 • EA Registration No. R22111378 (Ong Xin Yee)
By sending us your personal data and curriculum vitae (CV), you are deemed to consent to PERSOL Singapore Pte Ltd and its affiliates to collect, use and disclose your personal data for the purposes set out in the Privacy Policy available at ************* You acknowledge that you have read, understood, and agree with the Privacy Policy.
PERSOL is Asia-Pacific’s leading Staffing and HR solutions partner, operating across 13 markets with deep local insight and regional scale. With more than 80 offices and decades of experience, we deliver integrated workforce solutions that are tailored, tech-enabled, and designed for the dynamic world of work.
We combine human expertise with smart technology to help organisations solve workforce challenges, unlock potential, and stay ahead of change. From recruitment and talent management to workforce strategy and advisory, our collaborative approach puts your goals at the centre.
In 2025, we came together under the PERSOL name — reflecting our bold vision for the future of work and our Group’s Vision: Work and Smile.
Whether you’re building teams, growing careers, or transforming how work gets done, we’re here.
By sending us your personal data and curriculum vitae (CV), you are deemed to consent to PERSOL Singapore Pte Ltd and its local and overseas subsidiaries and affiliates to collect, use and disclose your personal data to prospective employers/companies based in any country for purposes of evaluating suitability for employment, conducting reference checks, administering employment related services, complying with Government’s health advisories and such other purposes stated in our Privacy Policy.
Our full Privacy Policy is available at ************* If you wish to withdraw your consent, please drop us an email at "*************" to let us know. Please feel free to contact us if you have any queries.
For more information, please visit *************
Develop complex circuit block, test key for leading-edge process node (planar, finfet, nanosheet) from schematic netlist to gds.
Develop standard cell library from architecture evaluation, PPA assessment and customized cell design with different PPA purpose and IP blocks.
Work with layout engineer for design implementation and physical verification including DRC/LVS/ERC/ANT.
Perform layout extraction, simulation, analyze simulation data, including performance, power, leakage, for layout dependent effect study.
Work with digital team and testing team for design implementation and chip level silicon data collection.
Develop processing flow for silicon data analysis, visualization, AI model regression.
Develop advanced library generation methodology and flow, including characterization, kit generation, regression, and quality assurance.
Perform timing/power/constraint/noise/LVF variation characterization for standard cell or complex circuit blocks.
Work with circuit designer and tool vendors to tackle modelling difficulties, like accuracy and runtime issues, especially for complex circuit blocks.
Responsible for new kits enablement and evaluation, like EM characterization, aging characterization.
Involve with data analysis and machine learning as well for circuit performance and power assessment.
Requirement:
Bachelor / Master’s Degree in Electrical and Electronic Engineering/Computer Engineering/Computer Science
Familiar with Python, Perl, Tcl or C/C++ for flow development and data analysis, machine learning.
Basic knowledge of digital design and/or circuit design.
Solid understanding of foundation IP design, with device physics, transistor level circuit, layout dependent effect knowledge.
Experience of test chip design in FinFet/Nanosheet technologies is a plus, with understanding of DRM, layout rules, PV check, and simulation skills.
Strong communication and teamwork skills to collaborate effectively with cross-functional teams.
Interested candidates may apply through the application system. We regret that only shortlisted candidates will be notified.
PERSOL Singapore Pte Ltd • UEN No. 200007268E • EA License No. 01C4394 • EA Registration No. R22111378 (Ong Xin Yee)
By sending us your personal data and curriculum vitae (CV), you are deemed to consent to PERSOL Singapore Pte Ltd and its affiliates to collect, use and disclose your personal data for the purposes set out in the Privacy Policy available at ************* You acknowledge that you have read, understood, and agree with the Privacy Policy.
PERSOL is Asia-Pacific’s leading Staffing and HR solutions partner, operating across 13 markets with deep local insight and regional scale. With more than 80 offices and decades of experience, we deliver integrated workforce solutions that are tailored, tech-enabled, and designed for the dynamic world of work.
We combine human expertise with smart technology to help organisations solve workforce challenges, unlock potential, and stay ahead of change. From recruitment and talent management to workforce strategy and advisory, our collaborative approach puts your goals at the centre.
In 2025, we came together under the PERSOL name — reflecting our bold vision for the future of work and our Group’s Vision: Work and Smile.
Whether you’re building teams, growing careers, or transforming how work gets done, we’re here.
By sending us your personal data and curriculum vitae (CV), you are deemed to consent to PERSOL Singapore Pte Ltd and its local and overseas subsidiaries and affiliates to collect, use and disclose your personal data to prospective employers/companies based in any country for purposes of evaluating suitability for employment, conducting reference checks, administering employment related services, complying with Government’s health advisories and such other purposes stated in our Privacy Policy.
Our full Privacy Policy is available at ************* If you wish to withdraw your consent, please drop us an email at "*************" to let us know. Please feel free to contact us if you have any queries.
For more information, please visit *************
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