Set up, troubleshoot, and recover complex downtime issues for test equipment, including Testcell, Tester, Bagger, VDCS, and Conveyor systems, with minimal supervision.
Proven experience leading and supporting Continuous Improvement Projects (CIP) to improve equipment performance, reduce downtime, enhance OEE, and optimize manufacturing processes.
Troubleshoot and resolve Testcell yield issues to maintain product quality, throughput, and equipment stability.
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Set up, troubleshoot, and recover complex downtime issues for test equipment, including Testcell, Tester, Bagger, VDCS, and Conveyor systems, with minimal supervision.
Proven experience leading and supporting Continuous Improvement Projects (CIP) to improve equipment performance, reduce downtime, enhance OEE, and optimize manufacturing processes.
Troubleshoot and resolve Testcell yield issues to maintain product quality, throughput, and equipment stability.
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Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning, layout construction, physical verification and QA flow sign-off.
Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project.
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