As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.
Experience in UVM verification methodology
Disciplined, quality-minded, and highly driven for excellence,
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Employer: Grace Orchard SchoolGrace Orchard School caters to students who have been diagnosed with Mild Intellectual Disability (MID) and those with Mild Autism Spectrum Disorders(ASD). The school is specifically for students ranging from 7-18 years old who have Intellectual Quotient (IQ) which falls within the range of 50-70. The school is a non- profit organisation under Presbyterian Community Social Services (PCS).
Job Description:
• Assist the class teacher in the preparation for daily teaching & learning activities and to present /reinforce learning concepts both in and outside school
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We are seeking a skilled Hardware FPGA Engineer to support the development of next-generation instrumentation and semiconductor test systems. In this role, you will be responsible for the specification, design, and verification of hardware and FPGA solutions, working closely with cross-functional teams to deliver high-performance and reliable test platforms for company’s global customers.
We are seeking an experienced Data Engineer to design, build, and optimize scalable data pipelines and architectures. The role focuses on ensuring reliable data integration, transformation, and accessibility across multiple platforms, including cloud environments, to support business intelligence and analytics initiatives.
Key Responsibilities
Design, develop, and maintain scalable data architectures and data pipelines based on business requirements
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As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.
Experience in UVM verification methodology
Disciplined, quality-minded, and highly driven for excellence,
...