Responsible for Physical Design tasks at block or subsystem level. The tasks will include Floorplanning, Synthesis, Placement, CTS, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.
Owning the entire process from SYN to PNR using Synopsys Fusion Compiler. Crafted the convergence recipe & design collateral to meet project requirement.
Run signoff flow including PV, extraction, STA, VCLP, FEV and EMIR, analyse the violation and converge the design.
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Regularly leads important projects that require providing experienced project team members with instruction, guidance, and advice in all aspects of the project to ensure delivery of quality outcomes.
Responsible for developing & reviewing project member software for automation machines to ensure requirement, functionality & expectation are fully covered.
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To lead technically in ASIC physical design domain, which may include stages from design specification understanding till layout and timing signoff for tapeout
To develop and signoff I.C. design projects physical design and flow improvement. Responsibilities include (as applicable)
Effective and efficient auto Place-and-Route implementation, covering floorplanning, PG mesh, placement, CTS, routing and chip-finishing
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Manage and coordinate IC Reliability (IC Rel) job submission processes, ensuring alignment with project timelines and quality gate requirements.
Develop and maintain capacity planning models for the IC Rel labs and testing equipment to optimize resource utilization and support BU forecast demands.
Serve as the primary interface between the Reliability Engineering team, Test Development, and Operations for all reliability test logistics and scheduling.
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