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Kerja Separuh Masa, VLSI Design Engineer | Physical Design Engineer | Design Verification Engineer di Software House Jobs & Internships - Maukerja

VLSI Design Engineer | Physical Design Engineer | Design Verification Engineer

Software House Jobs & Internships

Singapore

Kongsi
Simpan

Lokasi Kerja

  • Singapore

Penerangan Kerja

Tanggungjawab

Role Description

The VLSI Design Engineer / Physical Design Engineer / Design Verification Engineer develops and validates integrated circuits to meet functional, performance, power, and area requirements. Depending on the assigned specialization, the role involves designing digital logic and microarchitecture, implementing physical chip layouts, or verifying design behavior through simulation and formal methods.

The successful candidate will collaborate with architecture, RTL design, verification, and implementation teams to deliver reliable designs. This position also investigates design issues, evaluates results against specifications, and maintains documentation throughout the chip development lifecycle.


Qualifications
  • Bachelor’s degree in electrical engineering, electronics engineering, computer engineering, or a related field; an advanced degree is an advantage.
  • Relevant experience in VLSI design, physical design, or design verification, depending on the assigned specialization.
  • Strong understanding of digital logic, semiconductor fundamentals, and integrated circuit design flows.
  • For VLSI design positions, experience with microarchitecture, RTL coding, synthesis, and power, performance, and area optimization.
  • For physical design positions, experience with floorplanning, placement, clock tree synthesis, routing, and timing closure.
  • For physical design positions, familiarity with static timing analysis, parasitic extraction, power integrity, and physical verification.
  • For verification positions, experience developing testbenches, test plans, assertions, and functional coverage.
  • For verification positions, familiarity with SystemVerilog, UVM, constrained-random testing, and formal verification techniques.
  • Proficiency in Verilog, SystemVerilog, or VHDL, as relevant to the assigned role.
  • Familiarity with electronic design automation tools and scripting languages such as Python or Tcl.
  • Ability to debug complex issues, interpret tool results, and maintain reproducible workflows.
  • Strong analytical skills, attention to detail, and clear technical communication.
  • Ability to collaborate across engineering teams and meet project milestones.

Peringatan Penting

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