- Pulau Pinang Malaysia
Lokasi Kerja
Penerangan Kerja
Tanggungjawab
FPGA / RTL Design Engineer
We are looking for an FPGA / RTL Design Engineer to support RTL development, verification, FPGA implementation, and hardware bring-up. The ideal candidate has hands-on experience in Verilog/SystemVerilog, RTL design, and FPGA debugging.
Key Responsibilities
Key Requirements
Key Skills
FPGA, RTL Design, Verilog, SystemVerilog, ASIC Design, RTL Verification, FPGA Debugging, FPGA Bring-up, RTL Simulation, SoC Integration, Hardware Validation, Python, Perl, Tcl, Bash
Peringatan Penting
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