Kerja Sepenuh Masa, Senior Design Verification Engineer (FPGA-Emulation) di UST Pulau Pinang - Maukerja

Responsibilities

• Develop and execute verification plans for SoC/IP designs.
• Perform simulation, debugging, and functional verification.
• Support Emulation/FPGA-based verification.
• Write and debug C/C++ test code.
• Work closely with RTL/design teams to identify and resolve issues.

Requirements

• 4+ years of experience in Design Verification.
• Bachelor’s/Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or related field.
• Strong experience in SystemVerilog/UVM and DV methodologies.
• Hands-on experience with Emulation or FPGA is preferred.
• Proficiency in C/C++ programming.
• Experience with SoC/IP verification, debugging, and simulation tools.