- Toa Payoh Central Region (Singapore) Singapore
Kerja Sepenuh Masa DFT Engineer, Gaji tinggi SGD 10,000 di JUMPSTART DISRUPTIVE INNOVATIONS PTE. LTD. Central Region (Singapore) - Maukerja
DFT Engineer
JUMPSTART DISRUPTIVE INNOVATIONS PTE. LTD.
Kongsi
Simpan
Lokasi Kerja
Penerangan Kerja
Tanggungjawab
Job Description & Requirements
We are seeking an experienced DFT Engineer. The successful candidate will be responsible of:
DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST
Analysis to improve the testability of Digital design at Block and chip level.
Implementation of DFT logics for Digital and Mixed Signal IP.
Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern.
Perform ATPG verification and simulation playback
Deliver high quality ATE patterns for production ATE testing
Provide test pattern support to ATE engineering team for First Proto bring up and
failure analysis in the use of ATPG test and scan/debug features
Experience
Min 3 years of related working experience
Bachelor degree or equivalent in Electrical or Computer Engineering
Familiar with HDL design language
Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, cshell, Perl)
Knowledge of ASIC design is a must, and ATE test is a plus
Strong problem solving skills
Team player with strong communication skills
JDI is a Venture Catalyst driving forward the future of innovation.
We empower innovative companies to build, grow, and scale across Southeast Asia.
1) Tech JDI - Developing great tech solutions
2) Talent JDI – Growing human capital
3) Launch JDI – Accessing new markets
4) Capital JDI - Raising venture capital
5) Venture JDI - Building new ventures
Our clients range from fast-scaling start-ups to MNCS as well as Unicorns from industries such as e-commerce, cybersecurity, Fintech, F&B, Edtech, etc.
*************
We are seeking an experienced DFT Engineer. The successful candidate will be responsible of:
DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST
Analysis to improve the testability of Digital design at Block and chip level.
Implementation of DFT logics for Digital and Mixed Signal IP.
Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern.
Perform ATPG verification and simulation playback
Deliver high quality ATE patterns for production ATE testing
Provide test pattern support to ATE engineering team for First Proto bring up and
failure analysis in the use of ATPG test and scan/debug features
Experience
Min 3 years of related working experience
Bachelor degree or equivalent in Electrical or Computer Engineering
Familiar with HDL design language
Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, cshell, Perl)
Knowledge of ASIC design is a must, and ATE test is a plus
Strong problem solving skills
Team player with strong communication skills
JDI is a Venture Catalyst driving forward the future of innovation.
We empower innovative companies to build, grow, and scale across Southeast Asia.
1) Tech JDI - Developing great tech solutions
2) Talent JDI – Growing human capital
3) Launch JDI – Accessing new markets
4) Capital JDI - Raising venture capital
5) Venture JDI - Building new ventures
Our clients range from fast-scaling start-ups to MNCS as well as Unicorns from industries such as e-commerce, cybersecurity, Fintech, F&B, Edtech, etc.
*************
Peringatan Penting
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