Kerja Sepenuh Masa, Design Verification Engineer di UST Pulau Pinang - Maukerja

[Multiple Junior and Senior headcounts available in different specializations]

1. UVM & SV general
2. UVM & SV with PCIe / PCH
3. UVM & SV with USB
4. UVM & SV with IOHUB
5. UVM & SV with FPGA

Responsibilities:

1. Will be part of a team that handles Verification for complex IP’s and close the Verification to the challenging milestones.

2. IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation

3. Support in building verification infrastructure at the chip level as per the requirements

4. Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification

5. Working with the team and functional leads; Some interaction with cross functional groups

Job Requirements:

1. Have experience of digital IP verification with SV/UVM/Formal Verification or new methodology of the industry.

2. Good understanding of ASIC verification concepts and techniques and Verilog/System Verilog and UVM.

3. It’s a plus to be good at some script language, such as Perl, python. Or some database experience (for IP technical info maintain).

4. It’s also a plus if have experiences focusing on SV assertion/coverage/formal verification.

5. Bachelor’s degree or higher in Electrical and Electronics Engineering or related field

6. At least have a minimum of 4 years of relevant experience